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We will now add support for register-memory ALU operations to the classic five-stage RISC pipeline. To offset this increase in complexity, all memory

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asked 2021-02-25
We will now add support for register-memory ALU operations to the classic five-stage RISC pipeline. To offset this increase in complexity, all memory addressing will be restricted to register indirect (i.e., all addresses are simply a value held in a register; no offset or displacement may be added to the register value). For example, the register-memory instruction add x4, x5, (x1) means add the contents of register x5 to the contents of the memory location with address equal to the value in register x1 and put the sum in register x4. Register-register ALU operations are unchanged. The following items apply to the integer RISC pipeline:
a. List a rearranged order of the five traditional stages of the RISC pipeline that will support register-memory operations implemented exclusively by register indirect addressing.
b. Describe what new forwarding paths are needed for the rearranged pipeline by stating the source, destination, and information transferred on each needed new path.
c. For the reordered stages of the RISC pipeline, what new data hazards are created by this addressing mode? Give an instruction sequence illustrating each new hazard.
d. List all of the ways that the RISC pipeline with register-memory ALU operations can have a different instruction count for a given program than the original RISC pipeline. Give a pair of specific instruction sequences, one for the original pipeline and one for the rearranged pipeline, to illustrate each way.
Hint for (d): Give a pair of instruction sequences where the RISC pipeline has “more” instructions than the reg-mem architecture. Also give a pair of instruction sequences where the RISC pipeline has “fewer” instructions than the reg-mem architecture.

Answers (2)

2021-02-27
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Best answer
2021-09-09

a) The tradional five stage pipeline of IF, ID, EX, MEM, WB can be modified to IF,ID,MEM,EX,WB if we only wabt to support registe indirect addressing.

c) The following illustrates the forwarding path in the modified pipeline.

\(\begin{array}{|c|c|c|}\hline\text{Source Instruction Pipeline Stage}&\text{Destination Instruction Pipeline Stage}&\text{Remarks}\\\hline\text{MEM}&\text{MEM}&\text{Load or Store (data value or index)}\\\hline\text{EX}&\text{MEM}&\text{ALU OP producing the register for a Load or Store}\\\hline\text{EX}&\text{EX}&\text{Dependent ALU operation}\\\hline\end{array}\)

d) There are several ways that this modified ways that he modified ISA canhave a different instruction count for a given program over the original ISA. The modified pipeline enables the complier to mergeloads and ALU operations, there by reducing instruction count. However, these instructions cannot be merged if the memory operation requires an offset. If a memory operation requires anoff set and we are not able to merge it with abnother instruction, the modified ISA requires an additional instruction to compute the offset value and store it in a register.

Some examples:

\(\begin{array}{|c|c|c|}\hline\text{Original ISA}&\text{MODIFIED ISA}&\text{Remarks}\\\hline\text{LD,R2,16(R1)}&\text{ADDUI R3,R1,#16}&\text{Requires an additional instruction}\\\hline\text{LD R2,0(R1) ADD R3,R2,R4}&\text{ADD R3,R4,(R1)}&\text{Able to merge two instructions}\\\hline\end{array}\)

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